U.S. Pat. No. 4,620,294 relates to a dual speed, full duplex modem with a capability to transmit in the low speed asynchronous mode of 0-600 bits per second (b.p.s.) by coherent frequency shift keying (FSK), and to transmit in the high speed synchronous or asynchronous mode of 1200 b.p.s. by quadrature differential phase shift keying (QDPSR).
The present application relates to a multi-speed, full duplex modem, incorporating at least in part, the dual speed mode of application Ser. No. 530,690, with the addition of 2400 b.p.s. transmission speeds and adaptive equalization. One codec is used in the pending disclosure, and the separate multiplexer disclosed in the prior application is not used in the present application. An eight bit bi-directional bus is incorporated between the signal processor and the microcomputer in the present application, and a novel timing means is disclosed to enable the use of this eight bit bi-directional bus.
The novel features of this invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of an embodiment of the invention, when considered in conjunction with the accompanying drawings.